Modeling of simultaneous switching noise in high speed systems

IEEE International Symposium on Electromagnetic Compatibility

This paper discusses the modeling of simultaneous switching noise in high speed systems. Various methods have been presented and the accuracy of these methods bas been verified through measurements in both the frequency and time domain. These measurements include experimental test vehicles and functional products.

—This paper studies simultaneous switching noise (SSN) phenomenon in detail. The main objective of this work is the reduction of SSN. This is achieved firstly by adding the decoupling capacitors to check the paths impedance to ground and power planes. Then by using a proposed technique consisting to isolate the noisy components (digital circuits) of the sensitive components (analog circuits) by the addition of ground-reference planes with low noise. To analyze and quantify these different phenomena, the PSPICE simulations and the vector fitting method (VFM) are performed.

Electronic …, 2004

An analytical model of the coupling mechanism between the switching noises to signal traces has been successfully derived. The coupling mechanism was been rigorously analyzed and clarified. The analytical model was verified up to lOGHz by comparison with measured results and simulated results using a full wave simulator (HFSS). It has also been successfully applied to applications like the current memory modules (SDRAM DDR module).

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2000

In this paper, we introduce an application-specific device modeling methodology to develop simple device model that accurately tracks the actual device I-V characteristics in relevant but bounded operating regions. We have specifically used a simple MOSFET model to precisely analyze the switching noises generated on a chip due to simultaneous driving of chip output pads by bulky buffer gates. Previous works in analytical modeling of simultaneous switching noises employed long-channel and-power law transistor models; however, these models led to complex circuit equations that on truncation caused poor matching between manual analysis and actual simulation results. Also, in order to retain the simplicity of manual analysis, previous researchers ignored the parasitic capacitances of the bonding pads. This paper demonstrates that by using a simple application-specific transistor model, circuit equations can be solved precisely without requiring any gross approximations or model truncations, even when the inductance effects of bonding wires are simultaneously considered along with parasitic capacitances of the output pads. The analytical results derived in this paper tally with HSPICE simulation values within 3% deviations.

IEEE Transactions on Advanced Packaging, 2000

An accurate and analytical model for simultaneous switching noise (SSN) on ground lines in CMOS circuits is presented. This model can compute SSN for the case where only some drivers switch and the others remain quiet, that is, the model considers the loading effects on the quiet drivers. It was confirmed that the proposed model is more accurate than the existing ones through HSPICE simulation using the level 28 model for shortchannel MOSFET's. The proposed model can provide useful design guides for CMOS driver circuits.

date, 2002

In this paper, we study the simultaneous switching noise problem by using an application-specific modeling method. A simple yet accurate MOSFET model is proposed in order to derive closed-form formulas for simultaneous switching noise voltage waveforms. We first derive ...

Microelectronics Journal, 2004

Efficient prediction of the substrate noise generated by large digital sections is currently a major challenge in System-on-a-Chip design. A macromodel to accurately and efficiently predict the substrate noise generated by digital standard cells is presented. The macromodel is generated from identification of the physical elements relevant to noise generation. Techniques to directly or indirectly compute the values of the elements in the cell macromodel are proposed. Using this macromodel, prediction of the noise generated by large digital sections can be easily done following a methodology based on high-level logic simulation. As a first step to validation, the macromodel accuracy is demonstrated in some circuits consisting of a reduced number of gates.

Proceedings of the 5th Electronics Packaging Technology Conference (EPTC 2003)

This paper presents an analytical model of power/ground noise coupling to signal traces in high-speed multi-layer systems. The coupling model is expressed in terms of transfer impedance which denotes the coupled noise voltage at the signal trace when switching current occurs. This model is then compared with measured data and full-wave simulated data up to 10 GHz to verify the validity of the model. The results calculated by the proposed model shows good correlation with measurent.

Simultaneous switching noise (SSN) is a phenomenon with adverse and severe effects when a large number of high speed chip drivers switch simultaneously causing a large amount of current to be injected into the power distribution grid. The effects of SSN are manifested in a variety of transient and permanent system malfunctions including the appearance of undesirable glitches on what should otherwise be quiet signal lines and the flipping of state bits in registers and memories. Current approaches for dealing with SSN are largely ad hoc, relying primarily on the ability of expert designers to postulate worst-case scenarios for the occurrence of SSN-related errors and to analyze these scenarios using pessimistic estimates of packaging parasitics. This paper takes a first step toward evolving a systematic methodology for modeling and analysis of SSN in printed circuit boards (PCB's). The presented methodology adopts a combination of macro-and micro-models which allow for a system level treatment of the problem without losing the necessary detailed descriptions of the power/ground planes, the signal traces and the vertical interconnections through vias or plated holes. This approach has been applied to a variety of PCB structures and has allowed for an effective characterization of switching noise and a comprehensive understanding of its effects on PCB performance.

1996

A simplified laboratory eywiment representing simultaneouslj switching circuits in a multi-reference plane package is described.